Computer processor design is an extremely complex and lengthy process. The design process includes a range of tasks from high level tasks such as specifying the architecture down to low level tasks such as determining the physical placement of transistors on a silicon substrate. Each stage of the design process also involves extensive testing and verification of the design through that stage. One typical stage of processor design is to program the desired architecture for the processor using a register transfer language (RTL). The desired architecture is represented by an RTL specification that describes the behavior of the processor in terms of step-wise register contents. The RTL specification models what the processor does without describing the physical circuit details. Thus, the processor architecture can be verified at a high level with reference to the RTL specification, independent of implementation details such as circuit design and transistor layout. The RTL specification also facilitates later hardware design of the processor.
Manually verifying the RTL specification of the processor architecture is prohibitively complex during the design of a modern microprocessor. Therefore, multiple test cases are typically generated to test the design. Each test case contains input instructions and may also contain the desired results or outputs. Rather than running test cases through a simulation of the RTL specification and manually verifying the results, the test cases may be executed both on a simulation of the RTL specification (often compiled to increase speed) and on a “golden simulator” and the results compared. The golden simulator (GSIM) is a relatively-high level simulation of the processor architecture and therefore has a higher likelihood of accurately implementing the desired architecture than the RTL specification. The golden simulator may be implemented in any desired manner, such as a custom program written using a high-level programming language. Although the golden simulator is often a higher-level implementation of the processor architecture than the RTL specification, the golden simulator typically does go into enough detail to match the major structures in the RTL specification. For example, if the RTL specification describes a translation look aside buffer (TLB), the golden simulator may also implement a TLB to enable full testing and comparison of the RTL specification.
Test cases may thus be executed both on the RTL specification and the golden simulator, so that the results can be compared. Any difference in the results indicates an error in the RTL specification, the golden simulator, or both, although in theory the golden simulator is more likely to be error-free than the RTL specification.
In an actual processor, processing continues without end until the processor is powered down. In the case of processor verification testing, however, the test case must terminate at some point in time. Once the test case so terminates, there may be various transactions that are still pending. In particular, there may be transactions that were initiated during the testing but that did not complete as defined by finish criteria established for the given transactions. Although such pending transactions may be legitimate transactions, for instance transactions that were initiated after termination was asserted but during execution of a code sequence that is performed before all processing ceases, other pending transactions may comprise erroneous transactions that should have completed but did not due to an error. Therefore, a system and method for identifying such erroneous transactions is needed so that the existence of such errors can be identified to the processor designer.